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M41T62, M41T63 M41T64, M41T65
Serial Access Real-Time Clock with Alarms
FEATURES SUMMARY

350nA TIMEKEEPING CURRENT @ 3V TIMEKEEPING DOWN TO 1.0V 1.3V TO 3.6V I2C BUS OPERATING VOLTAGE COUNTERS FOR TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAY, DATE, MONTH, YEAR, AND CENTURY SERIAL INTERFACE SUPPORTS I2C BUS (400kHz) PROGRAMMABLE ALARM WITH FLAG BIT ONLY (M41T63/64) PROGRAMMABLE ALARM WITH FLAG BIT AND INTERRUPT FUNCTION (M41T62/65) LOW OPERATING CURRENT OF 35A SOFTWARE CLOCK CALIBRATION OSCILLATOR STOP DETECTION 32KHz SQUARE WAVE ON POWER-UP (M41T62/63/64) WATCHDOG TIMER WATCHDOG OUTPUT (M41T63/65) AUTOMATIC LEAP YEAR COMPENSATION OPERATING TEMPERATURE OF -40 TO 85C LEAD-FREE 16-PIN QFN PACKAGE TOTAL SURFACE AREA OF IC AND 32KHz CRYSTAL IS 21.5mm2
Figure 1. Package
QFN16 (Q) 3mm x 3mm
Figure 2. 32KHz Crystal + QFN16 vs. VSOJ20
VSOJ20 (47.6mm2)
2 GND Plane Guard Ring (21.5mm )
1
XI XO
SMT CRYSTAL
2 3 4
ST QFN16
AI11107
Table 1. Device Options
Basic RTC M41T62 M41T63 M41T64 M41T65 Alarms OSC Fail Detect Watchdog Timer Calibration SQW Output IRQ Output WDO Output F32K Output
May 2005
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M41T62/63/64/65
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. 32KHz Crystal + QFN16 vs. VSOJ20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. M41T62 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. M41T64 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. M41T63 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 6. M41T65 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 7. M41T62 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 8. M41T63 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 9. M41T64 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 10.M41T65 16-pin QFN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 11.M41T62 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 12.M41T63 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 13.M41T64 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 14.M41T65 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 15.Hardware Hookup for Battery Back-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 16.Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 17.Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 18.Slave Address Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 19.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 20.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 21.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TIMEKEEPER(R) Registers . . . . . . Table 3. M41T62 Register Map . . Table 4. M41T63 Register Map . . Table 5. M41T64 Register Map . . Table 6. M41T65 Register Map . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 13 . . . . 14 . . . . 15 . . . . 16 . . . . 17
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Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 22.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 23.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Watchdog Output (WDO - M41T63/65 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Square Wave Output (M41T62/63/64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 8. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Full-time 32KHz Square Wave Output (M41T64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output Driver Pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 9. Initial Power-on Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 25.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 26.Crystal Isolation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 16. Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 27.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 28.QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline . . . . . . . . 28 Table 18. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data . 29 Figure 29.QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint . . 30 Figure 30.32KHz Crystal + QFN16 vs. VSOJ20 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . 30 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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SUMMARY DESCRIPTION
The M41T6x Serial Access TIMEKEEPER(R) is a low power Serial RTC with a built-in 32.768 kHz oscillator (external crystal controlled). Eight registers (see Table 3., page 14) are used for the clock/ calendar function and are configured in binary coded decimal (BCD) format. An additional 8 registers provide status/control of Alarm, 32KHz output, Calibration, and Watchdog functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. Functions available to the user include a time-ofday clock/calendar, Alarm interrupts (M41T62/65), 32KHz output (M41T64), programmable Square Wave output (M41T62/63/64), and Watchdog output (M41T63/65). The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29- (leap year), 30- and 31-day months are made automatically. The M41T6x is supplied in a 16-pin QFN.
Figure 3. M41T62 Logic Diagram
VCC
Figure 5. M41T63 Logic Diagram
VCC
XI XO M41T62 SCL SDA SQW
(2)
XI IRQ/OUT
(1)
XO M41T63 SCL SDA
WDO(1) SQW(2)
VSS
Note: 1. Open Drain. 2. Defaults to 32KHz on power-up.
AI09103
VSS
Note: 1. Open Drain. 2. Defaults to 32KHz on power-up.
AI09189
Figure 4. M41T64 Logic Diagram
VCC
Figure 6. M41T65 Logic Diagram
VCC
XI XO M41T64 SCL SDA SQW F32K
(1)
XI XO M41T65
(2)
WDO(1) IRQ/FT/OUT(1)
SCL SDA
VSS
Note: 1. Open Drain. 2. Defaults to 32KHz on power-up.
AI09108
VSS
Note: 1. Open Drain.
AI09109
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M41T62/63/64/65
Figure 7. M41T62 16-pin QFN Connections
VCC NC NC NC
Figure 10. M41T65 16-pin QFN Connections
VCC 14 NC NC NC 13 12 11 10 9 5 6 NC 7 NC 8 NC NC IRQ/FT/OUT(1) SCL SDA
16 XI XO VSS SQW
(1)
15
14
13 12 11 10 9 NC IRQ/OUT(2) SCL SDA XI XO VSS WDO
(1)
16 1 2 3 4
15
1 2 3 4 5 VSS 6 NC 7 NC 8 NC
AI09100
VSS
AI09102
Note: 1. SQW Output will default to 32KHz upon power-up. 2. Open Drain.
Note: 1. Open Drain.
Table 2. Signal Names Figure 8. M41T63 16-pin QFN Connections
VCC NC NC NC
XI XO
Oscillator Input Oscillator Output Serial Data Input/Output Serial Clock Input Interrupt or OUT Output (Open Drain) Interrupt, Frequency Test, or OUT Output (Open Drain) Programmable Square Wave Defaults to 32KHz on Power-up (Open Drain for M41T64 only) Dedicated 32KHz Output (M41T64 only) Watchdog Timer Output (Open Drain) Supply Voltage Ground
16 XI XO VSS SQW
(1)
15
14
13 12 11 10 9 NC WDO(2) SCL SDA
1 2 3 4 5 VSS 6 NC 7 NC 8 NC
SDA SCL IRQ/OUT IRQ/FT/ OUT
AI09190
SQW
Note: 1. SQW Output will default to 32KHz upon power-up. 2. Open Drain.
F32K
Figure 9. M41T64 16-pin QFN Connections
VCC NC NC NC
WDO VCC
12 11 10 9 NC
16 XI XO VSS F32K
(1)
15
14
13
1 2 3 4 5 VSS 6 NC 7 NC 8 NC
VSS
SQW SCL SDA
(2)
AI09101
Note: 1. Enabled on power-up. 2. Open Drain.
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Figure 11. M41T62 Block Diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL OFIE DETECT RTC W/ALARM SDA WATCHDOG SQUARE WAVE SQWE SQW
(2) AI08899a
XTAL
AFE
IRQ/OUT
(1)
I2C INTERFACE
SCL
Note: 1. Open Drain. 2. Defaults to 32KHz on power-up.
Figure 12. M41T63 Block Diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL DETECT RTC W/ALARM SDA WATCHDOG SQUARE WAVE SQWE WDO SQW
(1)
XTAL
I2C INTERFACE
SCL
(2) AI09191
Note: 1. Open Drain. 2. Defaults to 32KHz on power-up.
Figure 13. M41T64 Block Diagram
32KE REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL DETECT RTC W/ALARM SDA WATCHDOG SQUARE WAVE SQWE SQW
(2) AI09192
F32K(1)
XTAL
I2C INTERFACE
SCL
Note: 1. Defaults enabled on power-up. 2. Open Drain.
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Figure 14. M41T65 Block Diagram
REAL TIME CLOCK CALENDAR 32KHz OSCILLATOR OSCILLATOR FAIL OFIE DETECT FT RTC W/ALARM SDA AFE IRQ/FT/OUT
(1)
XTAL
I2C INTERFACE
WATCHDOG
WDO(1)
AI09193
SCL
Note: 1. Open Drain.
Figure 15. Hardware Hookup for Battery Back-up Operation
VCC
(1) M41T6x VCC XI XO (2) IRQ/FT/OUT (3) WDO (4) SQW SCL VSS SDA F32K VCC Port Reset Input SQWIN Serial Clock Line Serial Data Line 32KHz CLKIN
AI10400
MCU
Note: 1. 2. 3. 4.
Diode required on open drain pin (M41T65 only) for battery (or SuperCap) back-up. Low threshold BAT42 diode recommended. For M41T62 and M41T65 (Open Drain). For M41T63 and M41T65 (Open Drain). For M41T64 (Open Drain).
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OPERATION
The M41T6x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 16 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Hours Register 5. Square Wave/Day Register 6. Date Register 7. Century/Month Register 8. Year Register 9. Calibration Register 10. Watchdog Register 11 - 15. Alarm Registers 16. Flags Register 2-Wire Bus Characteristics The bus is intended for communication between different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High. - Changes in the data line, while the clock line is High, will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy. Both data and clock lines remain High. Start data transfer. A change in the state of the data line, from high to Low, while the clock is High, defines the START condition. Stop data transfer. A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition. Data Valid. The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
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Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse Figure 16. Serial Bus Data Transfer Sequence
DATA LINE STABLE DATA VALID
in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 17. Acknowledgement Sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
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READ Mode In this mode the master reads the M41T6x slave after setting the slave address (see Figure 19., page 11). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T6x slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." Figure 18. Slave Address Location
R/W
This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-0Fh). Note: This is true both in READ Mode and WRITE Mode. An alternate READ Mode may also be implemented whereby the master reads the M41T6x slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 20., page 11).
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
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Figure 19. READ Mode Sequence
START START R/W BUS ACTIVITY: MASTER R/W
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 20. Alternative READ Mode Sequence
START R/W STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
NO ACK
ACK
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WRITE Mode In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is shown in Figure 21., page 12. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next Figure 21. WRITE Mode Sequence
START BUS ACTIVITY: MASTER R/W STOP WORD ADDRESS (An) ACK ACK DATA n DATA n+1 DATA n+X P ACK ACK
AI00591
and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T6x slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 18., page 10 and again after it has received the word address and each data byte.
SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
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M41T62/63/64/65
CLOCK OPERATION
The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768kHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The eight byte clock register (see Table 3., M41T62 Register Map, Table 4., M41T63 Register Map, Table 5., M41T64 Register Map, and Table 6., M41T65 Register Map) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers. Note: A WRITE to any clock register will result in the Tenths/Hundredths of Seconds being reset to "00," and Tenths/Hundredths of Seconds cannot be written to any value other than "00." Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month, and Years. The ninth clock register is the Calibration Register (this is described in the Clock Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical). Note: Upon initial power-up, the user should set the ST Bit to a '1,' then immediately reset the ST Bit to '0.' This provides an additional "kick-start" to the oscillator circuit. Bit D7 of Register 02h (Minute Register) contains the Oscillator Fail Interrupt Enable Bit (OFIE). When the user sets this bit to '1,' any condition which sets the Oscillator Fail Bit (OF) (see Oscillator Stop Detection, page 23) will also generate an interrupt output. Bits D6 and D7 of Clock Register 06h (Century/ Month Register) contain the CENTURY Bit 0 (CB0) and CENTURY Bit 1 (CB1). Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the OFIE Bit, RS0-RS3 Bit, and CB0-CB1 Bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These nonclock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. TIMEKEEPER (R) Registers The M41T6x offers 16 internal registers which contain Clock, Calibration, Alarm, Watchdog, Flags, and Square Wave. The Clock registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM TIMEKEEPER cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address (00h to 07h). The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to a non-clock address. TIMEKEEPER and Alarm Registers store data in BCD format. Calibration, Watchdog, and Square Wave Bits are written in a Binary Format.
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Table 3. M41T62 Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh OUT RB2 AFE RPT4 RPT3 RPT2 RPT1 WDF ST OFIE 0 RS3 0 CB1 0 RS2 0 CB0 10 Years 0 BMB4 SQWE RPT5 0 S BMB3 0 BMB2 Al 10M BMB1 0 D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format 10ths/100ths of Seconds Seconds Minutes Hours Day Date Century/ Month Year Calibration RB1 RB0 Watchdog Al Month Al Date Al Hour Al Min Al Sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 Hours RS1 RS0 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB0
10 Date 10M
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0
OF
0
Keys: 0 = Must be set to '0' AF = Alarm Flag (Read only) AFE = Alarm Flag Enable Flag BMB0 - BMB4 = Watchdog Multiplier Bits CB0-CB1 = Century Bits OF = Oscillator Fail Bit OFIE = Oscillator Fail Interrupt Enable Bit OUT = Output level
RB0 - RB2 = Watchdog Resolution Bits RPT1-RPT5 = Alarm Repeat Mode Bits RS0-RS3 = SQW Frequency Bits S = Sign Bit SQWE = Square Wave Enable Bit ST = Stop Bit WDF = Watchdog Flag Bit (Read only)
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Table 4. M41T63 Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 0 RB2 0 RPT4 RPT3 RPT2 RPT1 WDF ST 0 0 RS3 0 CB1 0 RS2 0 CB0 10 Years 0 BMB4 SQWE RPT5 0 S BMB3 0 BMB2 Al 10M BMB1 0 D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format 10ths/100ths of Seconds Seconds Minutes Hours Day Date Century/ Month Year Calibration RB1 RB0 Watchdog Al Month Al Date Al Hour Al Min Al Sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 Hours RS1 RS0 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB0
10 Date 10M
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0
OF
0
Keys: 0 = Must be set to '0' AF = Alarm Flag (Read only) BMB0 - BMB4 = Watchdog Multiplier Bits CB0-CB1 = Century Bits OF = Oscillator Fail Bit RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits RS0-RS3 = SQW Frequency Bits S = Sign Bit SQWE = Square Wave Enable Bit ST = Stop Bit WDF = Watchdog Flag Bit (Read only)
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Table 5. M41T64 Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 0 RB2 0 RPT4 RPT3 RPT2 RPT1 WDF ST 0 0 RS3 0 CB1 0 RS2 0 CB0 10 Years 0 BMB4 SQWE RPT5 0 S BMB3 32KE BMB2 Al 10M BMB1 0 D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format 10ths/100ths of Seconds Seconds Minutes Hours Day Date Century/ Month Year Calibration RB1 RB0 Watchdog Al Month Al Date Al Hour Al Min Al Sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 Hours RS1 RS0 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB0
10 Date 10M
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0
OF
0
Keys: 0 = Must be set to '0' 32KE = 32KHz Enable Bit AF = Alarm Flag (Read only) BMB0 - BMB4 = Watchdog Multiplier Bits CB0-CB1 = Century Bits OF = Oscillator Fail Bit RB0 - RB2 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits RS0-RS3 = SQW Frequency Bits S = Sign Bit SQWE = Square Wave Enable Bit ST = Stop Bit WDF = Watchdog Flag Bit (Read only)
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Table 6. M41T65 Register Map
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh OUT RB2 AFE RPT4 RPT3 RPT2 RPT1 WDF ST OFIE 0 0 0 CB1 0 0 0 CB0 10 Years FT BMB4 0 RPT5 0 S BMB3 0 BMB2 Al 10M BMB1 0 D6 D5 D4 D3 D2 D1 D0 Function/Range BCD Format 10ths/100ths of Seconds Seconds Minutes Hours Day Date Century/ Month Year Calibration RB1 RB0 Watchdog Al Month Al Date Al Hour Al Min Al Sec 0 Flags 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 00-23 01-7 01-31 0-3/01-12 00-99
0.1 Seconds 10 Seconds 10 Minutes 10 Hours 0 10 Date 10M 0 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB0
Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0
OF
0
Keys: 0 = Must be set to '0' AF = Alarm Flag (Read only) AFE = Alarm Flag Enable Flag BMB0 - BMB4 = Watchdog Multiplier Bits CB0-CB1 = Century Bits FT = Frequency Test Bit OF = Oscillator Fail Bit
OFIE = Oscillator Fail Interrupt Enable Bit OUT = Output level RB0 - RB2 = Watchdog Resolution Bits RPT1-RPT5 = Alarm Repeat Mode Bits S = Sign Bit ST = Stop Bit WDF = Watchdog Flag Bit (Read only)
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Calibrating the Clock The M41T6x is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The accuracy of the clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. The M41T6x oscillator is designed for use with a 6pF crystal load capacitance. When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature (see Figure 22., page 19). Therefore, the M41T6x design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 23., page 19. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Calibration Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower order bits (D4-D0) in the Calibration Register (08h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is
+4.068 or -2.034 PPM of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per day which corresponds to a total range of +5.5 or -2.75 minutes per month (see Figure 23., page 19). Two methods are available for ascertaining how much calibration a given M41T6x may require: - The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934, "TIMEKEEPER(R) CALIBRATION." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. - The second approach is better suited to a manufacturing environment, and involves the use of either the SQW pin (M41T62/63/64) or the IRQ/FT/OUT pin (M41T65). The SQW pin will toggle at 512Hz when RS3 = '0,' RS2 = '1,' RS1 = '1,' RS0 = '0,' SQWE = '1,' and ST = '0.' Alternatively, for the M41T65, the IRQ/FT/ OUT pin will toggle at 512Hz when FT and OUT Bits = '1' and ST = '0.' Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test or Square Wave output frequency.
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Figure 22. Crystal Accuracy Across Temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F K = -0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Temperature C
AI07888
Figure 23. Calibration Waveform
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
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Setting Alarm Clock Registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 7., page 20 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set (M41T62/65), the alarm condition activates the IRQ/OUT or IRQ/FT/ OUT pin. To disable the alarm, write '0' to the Alarm Date Register and to RPT5-RPT1. Figure 24. Alarm Interrupt Reset Waveform
0Eh 0Fh 00h
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ output is cleared by a READ to the Flags Register as shown in Figure 24., page 20. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.'
ALARM FLAG BIT (AF)
IRQ/OUT or IRQ/FT/OUT
HIGH-Z
AI08898
Table 7. Alarm Repeat Modes
RPT5 1 1 1 1 1 0 RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
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Watchdog Timer The watchdog timer can be used to detect an outof-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution where: 000=1/16 second (16Hz); 001=1/4 second (4Hz); 010=1 second (1Hz); 011=4 seconds (1/4Hz); and 100 = 1 minute (1/60Hz). Note: Invalid combinations (101, 110, and 111) will NOT enable a watchdog time-out. Setting the BMB4-BMB0 = 0 with any combination of RB2RB0, other than 000, will result in an immediate watchdog time-out. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds). If the processor does not reset the timer within the specified period, the M41T6x sets the WDF (Watchdog Flag) and generates an interrupt on the IRQ pin (M41T62), or a watchdog output pulse (M41T63 and M41T65 only) on the WDO pin. The watchdog timer can only be reset by having the microproces-
sor perform a WRITE of the Watchdog Register. The time-out period then starts over. Should the watchdog timer time-out, any value may be written to the Watchdog Register in order to clear the IRQ pin. A value of 00h will disable the watchdog function until it is again programmed to a new value. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up, and the Watchdog Register is cleared. Note: A WRITE to any clock register will restart the watchdog timer. Watchdog Output (WDO - M41T63/65 only) If the processor does not reset the watchdog timer within the specified period, the Watchdog Output (WDO) will pulse low for trec (see Table 17., page 27). This output may be connected to the Reset input of the processor in order to generate a processor reset. After a watchdog time-out occurs, the timer will remain disabled until such time as a new countdown value is written into the watchdog register. Note: The crystal oscillator must be running for the WDO pulse to be available. The WDO output is an N-channel, open drain output driver (with IOL as specified in Table 14., page 26).
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Square Wave Output (M41T62/63/64) The M41T62/63/64 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 04h establish the square wave output frequency. These frequencies are listed in Table 8. Once the selection of the SQW frequency has been completed, the SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah. Table 8. Square Wave Output Frequency
Square Wave Bits RS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Square Wave Frequency None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1 Units - kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
The SQW output is an N-channel, open drain output driver for the M41T64, and a full CMOS output driver for the M41T62/63. The initial power-up default for the SQW output is 32KHz (except for M41T64, which defaults disabled).
Full-time 32KHz Square Wave Output (M41T64) The M41T64 offers the user a special 32KHz square wave function which is enabled on powerup to output on the F32K pin as long as VCC 1.3V, and the oscillator is running (ST Bit = '0'). This function is available within one second (typ) of ini-
tial power-up and can only be disabled by setting the 32KE Bit to '0' or the ST Bit to '1.' If not used, the F32K pin should be disconnected and allowed to float.
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Century Bits These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See Table 10., page 23 for additional explanation. Output Driver Pin (M41T62/65) When the OFIE Bit, AFE Bit, and watchdog register are not set to generate an interrupt, the IRQ/ OUT pin becomes an output driver that reflects the contents of D7 of the Calibration Register. In other words, when D7 (OUT Bit) is a '0,' then the IRQ/ OUT pin will be driven low. Note: The IRQ/OUT pin is an open drain which requires an external pull-up resistor. Oscillator Stop Detection If the Oscillator Fail (OF) Bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. This bit will be set to '1' any time the oscillator stops. In the event the OF Bit is found to be set to '1' at any time other than the initial power-up, the STOP Bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator.
The following conditions can cause the OF Bit to be set: - The first time power is applied (defaults to a '1' on power-up). Note: If the OF Bit cannot be written to '1' four (4) seconds after the initial power-up, the STOP Bit (ST) should be written to a '1,' then immediately reset to '0.' - The voltage present on VCC or battery is insufficient to support oscillation. - The ST Bit is set to '1.' - External interference of the crystal If the Oscillator Fail Interrupt Enable Bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The IRQ output is cleared by resetting the OFIE or OF Bit to '0' (NOT by reading the Flag Register). The OF Bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF Bit to '0.' If the trigger event occurs during a powerdown condition, this bit will be set correctly. Initial Power-on Defaults Upon application of power to the device, the register bits will initially power-on in the state indicated in Table 9.
Table 9. Initial Power-on Default Values
Condition Device M41T62 Initial Power-up(1) M41T63 M41T64 M41T65 ST 0 0 0 0 OF 1 1 1 1 OFIE 0 N/A N/A 0 OUT 1 N/A N/A 1 FT N/A N/A N/A 0 AFE 0 N/A N/A 0 SQWE 1 1 0 N/A 32KE N/A N/A 1 N/A RS3-1 0 0 0 N/A RS0 1 1 1 N/A Watchdog 0 0 0 0
Note: 1. All other control bits power-up in an undetermined state.
Table 10. Century Bits Examples
CB0 0 0 1 1 CB1 0 1 0 1 Leap Year? Yes No No No Example(1) 2000 2100 2200 2300
Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
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MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 11. Absolute Maximum Ratings
Sym TSTG VCC TSLD
(3)
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Parameter Storage Temperature (VCC Off, Oscillator Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Robotic Charged Device Model)
Conditions(1)
Value(2) -55 to 125 -0.3 to 4.6 260 -0.2 to Vcc+0.3 20 1
Unit C V C V mA W V V
VIO IO PD VESD(HBM) VESD(RCDM)
TA = 25C TA = 25C
>1000 >1000
Note: 1. Test conforms to JEDEC standard. 2. Data based on characterization results, not tested in production. 3. Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
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DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
M41T6x 1.3V to 3.6V -40 to 85C 50pF 5ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Figure 25. AC Measurement I/O Waveform
Figure 26. Crystal Isolation Example
Local Grounding Plane (Layer 2)
XI
0.8VCC
Crystal 0.7VCC 0.3VCC
AI02568 XO GND
0.2VCC
AI09127
Note: Substrate pad should be tied to VSS.
Table 13. Capacitance
Symbol CIN COUT(3) tLP Input Capacitance Output Capacitance Low-pass filter input time constant (SDA and SCL) Parameter(1,2) Min Max 7 10 50 Unit pF pF ns
Note: 1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected.
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Table 14. DC Characteristics
Sym Parameter Test Condition(1) Clock(2) I2C bus (400kHz) 3.6V ICC1 Supply Current SCL = 400kHz (No load) 3.0V 2.5V 2.0V SCL = 0Hz All inputs VCC - 0.2V VSS + 0.2V 3.6V SQW Off 3.0V @ 25C 2.0V @ 25C -0.2 0.7VCC VCC = 3.6V, IOL = 3.0mA (CMOS or Open Drain) VCC = 3.6V, IOL = 1.0mA (SQW, WDO, IRQ) VCC = 3.6V, IOH = -1.0mA (Push-Pull) IRQ/OUT, IRQ/FT/OUT, WDO, SQW (M41T64 only) 0V VIN VCC 0V VOUT VCC 2.4 3.6 1 1 Min 1.0 1.3 50 35 30 20 375 350 310 0.3VCC VCC+0.3 0.4 0.4 700 Typ Max 3.6 3.6 100 Unit V V A A A A nA nA nA V V V V V V A A
VCC(3) Operating Voltage
ICC2
Supply Current (standby)
VIL VIH
Input Low Voltage Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage Pull-up Supply Voltage (Open Drain)
ILI ILO
Input Leakage Current Output Leakage Current
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.3V to 3.6V (except where noted). 2. Oscillator start-up guaranteed at 1.5V only. 3. When using battery back-up, VCC fall time should not exceed 10mV/s.
Table 15. Crystal Electrical Characteristics
Sym fO RS CL Parameter(1,2) Resonant Frequency Series Resistance Load Capacitance 6 Min Typ 32.768 65(3) Max Units kHz k pF
Note: 1. Externally supplied if using the QFN16 package. STMicroelectronics recommends the Citizen CFS-145 (1.5x5mm) and the KDS DT-38 (3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surface-mount, tuning fork-type quartz crystals. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp. Citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com. 2. Load capacitors are integrated within the M41T6x. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. Guaranteed by design.
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Table 16. Oscillator Characteristics
Symbol Parameter Oscillator Start Voltage Oscillator Start Time XIN XOUT IC-to-IC Frequency Variation (1) -10 Conditions 10 seconds VCC = 3.0V 12 12 +10 Min 1.5 1 Typ Max Unit V s pF pF ppm
VSTA
tSTA Cg Cd
Note: 1. Reference value. T A = 25C, VCC = 3.0V, CMJ-145 (CL = 6pF, 32,768Hz) manufactured by Citizen.
Figure 27. Bus Timing Requirements Sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
Table 17. AC Characteristics
Sym fSCL tLOW tHIGH tR tF tHD:STA tSU:STA tSU:DAT(2) tHD:DAT tSU:STO tBUF trec Parameter(1) SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time Data Hold Time STOP Condition Setup Time Time the bus must be free before a new transmission can start Watchdog Output Pulse Width 600 600 100 0 600 1.3 96 98 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns ns ns s ns s ms
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 1.3 to 3.6V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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M41T62/63/64/65
PACKAGE MECHANICAL INFORMATION
Figure 28. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline
D
E
A3
A1
A
ddd C
b L
e K
1 2
E2
3
Ch
K D2
QFN16-A
Note: Drawing is not to scale.
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M41T62/63/64/65
Table 18. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data
mm Symb Typ A A1 A3 b D D2 E E2 e K L ddd Ch N 0.90 0.02 0.20 0.25 3.00 1.70 3.00 1.70 0.50 0.20 0.40 - - Min 0.80 0.00 - 0.18 2.90 1.55 2.90 1.55 - - 0.30 0.08 0.33 16 Max 1.00 0.05 - 0.30 3.10 1.80 3.10 1.80 - - 0.50 - - Typ 0.035 0.001 0.008 0.010 0.118 0.067 0.118 0.067 0.020 0.008 0.016 - - Min 0.032 0.000 - 0.007 0.114 0.061 0.114 0.061 - - 0.012 0.003 0.013 16 Max 0.039 0.002 - 0.012 0.122 0.071 0.122 0.071 - - 0.020 - - inches
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M41T62/63/64/65
Figure 29. QFN16 - 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint
1.60
3.55
2.0
AI09126
Note: Dimensions shown are in millimeters (mm).
0.28
Figure 30. 32KHz Crystal + QFN16 vs. VSOJ20 Mechanical Data
7.0 0.3
VSOJ20
6.0 0.2 3.2
1
XI XO
SMT CRYSTAL
2 3 4
2.9
ST QFN16
1.5
Note: Dimensions shown are in millimeters (mm).
2.9
AI11146
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M41T62/63/64/65
PART NUMBERING
Table 19. Ordering Information Scheme
Example: M41T 62 Q 6 F
Device Family M41T
Device Type and Supply Voltage 62 = VCC = 1.3V to 3.6V 63 = VCC = 1.3V to 3.6V 64 = VCC = 1.3V to 3.6V 65 = VCC = 1.3V to 3.6V
Package Q = QFN16
Temperature Range 6 = -40C to 85C
Shipping Method for SOIC F = Lead-free Package, Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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M41T62/63/64/65
REVISION HISTORY
Table 20. Document Revision History
Date November 13, 2003 19-Nov-03 25-Dec-03 14-Jan-04 27-Feb-04 02-Mar-04 26-Apr-04 13-May-04 06-Aug-04 11-Oct-04 18-Jan-05 05-May-05 Version 1.0 1.1 2.0 2.1 2.2 2.3 3.0 4.0 5.0 6.0 7.0 8.0 First Issue Add features, update characteristics (Figure 3, 4, 6, 11, 24; Table 2, 3, 9, 11, 14, 17) Reformatted; add crystal isolation, footprint (Figure 26) Update characteristics (Figure 3, 11, 26; Table 1, 3. 9, 14) Update characteristics and mechanical dimensions (Figure 3, 4, 5, 6, 7, 8, 11, 12, 13, 14, 28, 29; Table 3, 4, 5, 6, 9, 11, 14, 18) Update characteristics (Figure 9, 10, 13; Table 2, 14) Reformat and republish Update characteristics (Figure 7, 8, 9, 10, 26, 29; Table 11, 14, 15) Correct diagrams; update characteristics (Figure 4, 5, 26; Table 2, 14, 16) Update characteristics (Table 11, 14) Correct footprint dimensions; update characteristics (Figure 4, 9, 13, 15, 29; Table 1, 2, 5, 8, 9, 11, 12, 14, 15, 16, 17) Add package comparison and mechanical data (Figure 2, 30) Revision Details
M41T6x, 41T6X, T6X, T62, T63, T64, T65, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Programmable Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Alarm, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, Watchdog, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Write Protect, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, vIndustrial, Industrial, Industrial, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
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M41T62/63/64/65
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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